The present invention relates to a semiconductor wafer and a method for manufacturing a semiconductor device utilizing the same.
With the recent trend for higher integration of LSIs, the technique of aligning a mask with a semiconductor wafer in the photolithography step is becoming very important. This will be described with reference to a MOS transistor of the structure shown in FIG. 1. Referring to FIG. 1, n.sup.+ -type source and drain regions 2 and 3 are formed in a p-type semiconductor substrate 1 as electrically insulated from each other. A gate electrode 5 is formed through a gate oxide film 4 on a channel region between the source and drain regions 2 and 3. An insulating oxide film 6 is formed over the entire surface of the structure. An aluminum wiring 8 or the like for the drain region 3 is formed through a contact hole 7 formed in the insulating oxide film 6. In a MOS transistor of this structure, alignment of the gate electrode 5 with the contact hole 7 is very important for achieving higher integration of an LSI. In other words, care must be taken so as not to cause short-circuiting between the gate electrode 5 and the drain region 3 and so as not to bring the gate electrode 5 into contact with the aluminum wiring 8 in the contact hole 7. In order to achieve this, a gap A must be guaranteed between the gate electrode 5 and the contact hole 7. In forming this gap A, a sufficient alignment margin must be allowed so as to avoid short-circuiting between the gate and source regions even though the mask for forming the contact hole 7 is misaligned with the gate electrode 5. If the alignment precision is not good, the size of gap A must be made great, thus interfering with higher integration of LSIs.
A conventional wafer alignment technique will be described with reference to a step and repeat exposure apparatus of the type shown in FIG. 2. Referring to FIG. 2, a stage 11 movable in the directions of the X- and Y-axes holds a wafer chuck 12. An optical column 13 incorporating an optical system for reducing the mask pattern in scale is arranged above the stage 11. Two alignment marks 14a and 14b as references for alignment with alignment marks 23a and 23b on a mask 22 are arranged at the upper end face of the optical column 13. A light source 15 is arranged above the optical column 13 with a predetermined distance therebetween. An alignment system 16 is attached to the side surface of the optical column 13. The alignment system 16 comprises a main body 17 which has, at its bottom, alignment marks 18a and 18b for alignment with the alignment marks of the mask, and microscopes 19a and 19b which are mounted on the main body 17 and which are used for observation of the registration state of alignment marks 25a and 25b on a wafer 24 with the alignment marks 18a and 18b. In some alignment systems of this type, a mirror or a half mirror is interposed between the alignment marks 18a and 18b and the microscopes 19a and 19b. In this case, an alignment monitor 20 may be incorporated for facilitating observation of the registration state of the alignment marks on the wafer with the alignment marks 18a and 18b. Alignment marks 21 and 21' are attached to the side surfaces of the stage 11 and the optical column 13, respectively, for alignment of these members in the direction of the Y-axis.
A method for mask alignment and exposure of a mask with a step and repeat exposure apparatus of the reduction projection type will now be described below.
A mask 22 is aligned with the optical column 13 by aligning the alignment marks 23a and 23b on the mask 22 with the alignment marks 14a and 14b attached on the upper end face of the optical column 13. During this mask alignment step, the pattern of the mask 22 is reduced in scale by the reduction projection type optical system, and the misalignment between the mask 22 and the optical column 13 is also reduced in scale. For this reason, this misalignment becomes almost negligible. After the wafer 24 is placed on the wafer chuck 12, the alignment marks 25a and 25b on the wafer 24 are aligned with the alignment marks 18a and 18b on the main body 17 by moving the wafer 24 while observing through the microscopes 19a and 19b of the alignment system 16 or while monitoring the alignment monitor 20. Upon completing alignment of the alignment marks 18a and 18b of the alignment system 16 with the alignment marks 25a and 25b of the wafer 24, the wafer 24 is aligned relative to the optical column 13 and the mask 22. This is because the alignment system 16 is fixed in position relative to the optical column 13. After alignment of the mask 22 with the wafer 24, the stage 11 is moved on rails (not shown) in the Y-axis direction to locate the wafer 24 immediately below the optical column 13 as indicated by dotted lines in FIG. 2. Alignment of the stage 11 with the optical column 13 in the Y-axis direction is automatically performed with a laser interferometer utilizing the alignment marks 21 and 21' on the stage 11 and on the optical column 13. The wafer 24 is moved around in a preprogrammed step and repeat format in the X- and Y-axis directions together with the stage 11. In each step, the mask 22 is exposed to light emitted from the light source 15. The light carrying the information on the mask pattern is supplied to the optical column 13 to be reduced thereby in scale. In this manner, the reduced mask patterns are repeatedly formed on predetermined regions 26 on the wafer 24 as shown in FIG. 3. After completing exposure of the mask 22 to light, the stage 11 is returned to the original position (where it was aligned with the wafer 24), and is replaced with a new wafer.
However, the exposure method described above presents the problems to be described below with reference to alignment of the wafer 24 with the alignment system 16.
In order to obtain satisfactory alignment precision, the alignment marks 25a and 25b of the wafer 24 of very small sizes cannot be used and must have the sizes of about 130 .mu.m.times.130 .mu.m. Furthermore, the alignment marks 25a and 25b are generally attached at the center of the wafer 24 with a predetermined gap B therebetween. Then, this portion of the wafer 24 cannot be supplied for production of chip patterns, so that the yield of LSIs from wafers is reduced. This is because superposition of the chip pattern on the alignment marks 25a and 25b results in hard identification of the alignment marks 25a and 25b and hence in a degradation in the alignment precision. This problem similarly recurs in manual and automatic mask alignment procedures.
Even if the chip pattern is not formed on the alignment marks 25a and 25b of the wafer 24, when the alignment mark 25 is formed by etching of an oxide film 27 on the wafer 24, and various films 28 and 29 (especially the film 29 of a material which is easy to melt) are deposited on the oxide film 27 as shown in FIG. 4, the steps of the alignment mark 25 is eliminated and detection of this alignment mark 25 is thus impaired. In order to avoid this problem, the films 28 and 29 on the alignment mark 25 must be selectively etched. This results in a complex mask alignment procedure and a low yield of semiconductor devices. It is also known to form new alignment marks with the chip pattern in the second step and thereafter. The alignment marks are formed, in this case, in alignment with the chip pattern according to one method or with wafer regions other than the chip pattern according to another method. The former method results in restriction of reduction in scale of the chip pattern or design limitations of the LSI pattern since the alignment marks are formed in alignment with each chip pattern. Although the alignment marks need not be formed within the chip according to the latter method, a separate mask is required, resulting in a complex structure of the exposure apparatus and in a complex manufacturing procedure.
The manufacturing process of LSIs is increasingly automated due to rapid advances in the LSI-related technology. Automation of the LSI manufacturing process provides various advantageous. To mention some of these advantages, the manufacturing cost is reduced due to savings in labor, manual errors are eliminated, variations in the characteristics of devices produced due to slight differences in steps introduced by manual labor are eliminated, and the manufacturing yield is improved since dust-proof devices may be produced without requiring employees to work in a clean room.
Automation of the LSI manufacturing process may be achieved by the methods to be described below. As shown in FIG. 5, an information mark 30 (11-6) is formed on the surface of the wafer 24 with a laser beam or the like. Numeral "11" in the information mark 30 designates the lot # and numeral "6" designates the wafer number. Prior to each step for manufacturing a semiconductor device, the information mark 30 on the wafer 24 is read. In accordance with the read information on the wafer 24, a computer storing a control program generates instructions to perform suitable processing in each step. However, if chip patterns or various films are formed on the information mark 30, it becomes difficult to read the information mark 30, as in the case of the mask alignment technique utilizing the alignment marks described above. Furthermore, the wafers 24 are usually stood vertically next to each other on a boat or the like. Therefore, in order to read the information mark 30 on the wafer 24 shown in FIG. 5, the wafers 24 thus stored must be individually taken out of the boat, thus impairing the automatic reading operation.